My research is in the area of Software for Embedded Systems. I am currently investigating issues related to Real-Time Operating System (RTOS) synthesis, high-confidence embedded software, serializing compilers, and algorithmic code transformation techniques targeting embedded software.
B2. A. Nacul, M. Lajolo, T. Givargis.
Interface-Centric Abstraction level for Rapid Hardware/Software Integration, Book Chapter in Applications of Specification And Design Languages for SOCs.
Springer, ISBN: 1-4020-4997-8, July 2006.
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B1. F. Vahid, T. Givargis.
Embedded System Design: A Unified Hardware/Software Introduction.
John Wiley and Sons, ISBN: 0471386782, October 2001.
Journal
J16. A. Nacul, T. Givargis.
Synthesis of Time-Constrained Multitasking Embedded Software.
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 11, no.4, pp. 822-847, October 2006.
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J15. M.A. Ghodrat, T. Givargis, A. Nicolau.
Expression Equivalence Checking using Interval Analysis.
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 14, no. 8, pp. 830-842, August 2006.
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J14. C.V. Lopes, A. Haghighat, A. Mandal, T. Givargis, P. Baldi.
Localization of Off-the-Shelf Mobile Devices Using Audible Sound: Architectures, Protocols and Performance Assessment.
ACM Mobile Computing and Communications Review (MC2R), vol. 10, no. 2, pp. 38-50, April 2006.
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J13. T. Givargis.
Zero Cost Indexing for Improved Embedded Processor Cache Performance.
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 11, no. 1, pp. 3-25, January 2006. Received the 2006 TODAES Best Paper Award.pdf
J12. T. Givargis, D. Eppstein.
Memory Reference Caching for Activity Reduction on Address Buses.
Elsevier Journal of Microprocessors and Microsystems (MICPRO), vol. 29, no. 4, pp. 145-153, May 2005.
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J11. A. Ghosh, T. Givargis.
Cache Optimization for Embedded Processor Cores: An Analytical Approach.
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 9, no. 4, pp. 419-440, October 2004.
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J10. A. Nacul, T. Givargis.
Adaptive Cache Management for Low Power Embedded Systems.
Korea Multimedia Society, Key Technology of Next Generation IT, ISSN 1229-778X, pp. 30-39, December 2003.
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J9. T. Givargis, F. Vahid, J. Henkel.
Instruction-Based System-level Power Evaluation of System-on-a-Chip Peripheral Cores.
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 10, no. 6, pp. 856-863, December 2002.
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J8. T. Givargis, F. Vahid, J. Henkel.
System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-a-Chip.
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 10, no. 4, pp. 416-422, December 2002.
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J7. T. Givargis, F. Vahid.
Platune: A Tuning Framework for System-on-a-Chip Platforms.
IEEE Transactions on Computer Aided Design (TCAD), vol. 21, no. 11, pp. 1317-1327, November 2002.
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J6. F. Vahid, T. Givargis, S. Cotterell.
Power Estimator Development for Embedded System Memory Tuning.
Journal of Circuits, Systems, and Computers (JCSC), vol. 11, no. 5, pp. 459-476, October 2002.
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J5. T. Givargis, F. Vahid.
Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms.
Kluwer Journal on Design Automation of Embedded Systems, vol. 7, issue 1-2, pp. 35-51, September 2002.
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J4. T. Givargis, F. Vahid, J. Henkel.
Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs.
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 9, no. 4, pp. 500-508, August 2001.
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J3. F. Vahid, T. Givargis.
Platform Tuning for Embedded Systems Design.
IEEE Computer, vol. 34, no. 3, pp. 112-114, March 2001.
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J2. J. Farrell, T. Givargis, M. Barth.
Real-Time Differential Carrier Phase GPS-Aided INS.
IEEE Transactions on Control Systems Technology (TCST), vol. 8, no. 4, pp. 709-721, July 2000.
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J1. J. Farrell, T. Givargis.
Differential GPS Reference Station Algorithm - Design and Analysis.
IEEE Transactions on Control Systems Technology (TCST), vol. 8, no. 3, pp. 519-531, May 2000.
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Conference
C37. M. Ghodrat, T. Givargis, A. Nicolau.
Control Flow Optimization in Loops using Interval Analysis.
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), to appear.
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C36. F. Vahid, T. Givargis.
Highly-Cited Ideas in System Codesign and Synthesis.
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), to appear.
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C35. S. Choudhuri, T. Givargis.
Deterministic Service Guarantees for NAND Flash using Partial Block Cleaning.
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), to appear.
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C34. S. Choudhuri, T. Givargis.
Real-Time Access Guarantees for NAND Flash using Partial Block Cleaning.
Workshop on Software Technologies for Future Embedded & Ubiquitous Systems (SEUS), to appear.
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C33. A. Ghosh, T. Givargis.
A Software Architecture for Accessing Data in Sensor Networks.
International Conference on Networked Sensing Systems (INSS), pp. 67-70, Japan, June 2008.
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C32. S. Choudhuri, T. Givargis.
Performance Improvement of Block Based NAND Flash Translation Layer.
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 257-262, Salzburg, September 2007.
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C31. M.A. Ghodrat, T. Givargis., A. Nicolau.
Short-Circuit Compiler Transformation: Optimizing Conditional Blocks.
Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 504-510, Tokyo, January 2007.
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C30. S. Choudhuri, T. Givargis.
System Architecture for Software Peripherals.
Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 56-61, Tokyo, January 2007.
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C29. A. Nacul, T. Givargis.
Phantom: A Serializing Compiler for Multitasking Embedded Software.
American Control Conference (ACC), Minneapolis, June 2006. Received a 2006 ACC Best Paper Award.pdf
C28. M.A. Ghodrat, T. Givargis, A. Nicolau.
Equivalence Checking of Arithmetic Expressions using Fast Evaluation.
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 147-156, San Francisco, September 2005.
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C27. A. Nacul, T. Givargis.
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler.
Design Automation and Test in Europe (DATE), pp. 740-747, Munich, March 2005.
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C26. A. Ghosh, T. Givargis.
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks.
Design Automation and Test in Europe (DATE), pp. 190-195, Munich, March 2005.
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C25. A. Mandal, C.V. Lopes, T. Givargis, A. Haghighat, R. Jurdak, P. Baldi.
Beep: 3D Indoor Positioning Using Audible Sound.
IEEE Consumer Communications and Networking Conference (CCNC), pp. 348-353, Las Vegas, January 2005.
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C24. A. Nacul, T. Givargis.
Code Partitioning for Synthesis of Embedded Applications with Phantom.
International Conference on Computer-Aided Design (ICCAD), pp. 190-196, San Jose, November 2004.
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C23. A. Nacul, T. Givargis.
Dynamic Voltage and Cache Reconfiguration for Low Power.
Design Automation and Test in Europe (DATE), pp. 1376-1377, Paris, February 2004.
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C22. M. Buss, T. Givargis, N. Dutt.
Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores.
Real-Time Systems Symposium (RTSS), pp. 275-281, Cancun, December 2003.
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C21. A. Ghosh, T. Givargis.
Cache Optimization for Embedded Processor Cores: An Analytical Approach.
International Conference on Computer-Aided Design (ICCAD), pp. 342-347, San Jose, November 2003.
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C20. T. Givargis.
Improved Indexing for Cache Miss Reduction in Embedded Systems.
Design Automation Conference (DAC), pp. 872-880, Anaheim, June 2003.
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C19. A. Ghosh, T. Givargis.
Analytical Design Space Exploration of Caches for Embedded Systems.
Design Automation and Test in Europe (DATE), pp. 650-655, Munich, March 2003.
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C18. T. Givargis, D. Eppstein.
Reference Caching Using Unit Distance Redundant Codes for Activity Reduction on Address Buses.
International Workshop on Embedded System Hardware/Software Codesign (ESCODES), San Jose, September 2002.
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C17. M. Palesi, T. Givargis.
Multi-Objective Design Space Exploration Using Genetic Algorithms.
International Workshop on Hardware/Software Codesign (CODES), Estes Park, May 2002.
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C16. T. Givargis, F. Vahid, J. Henkel.
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip.
International Conference on Computer-Aided Design (ICCAD), San Jose, November 2001.
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C15. T. Givargis, F. Vahid. J. Henkel.
Trace-Driven System-Level Power Evaluation of System-on-a-Chip Peripheral Cores.
Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, January 2001.
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C14. G. Stitt, F. Vahid, T. Givargis, R. Lysecky.
A First-Step Towards an Architecture Tuning Methodology.
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), San Jose, November 2000.
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C13. T. Givargis, F. Vahid, J. Henkel.
Instruction-Based System-Level Power Evaluation of System-on-a-ChipPeripheral Cores.
International Symposium on System Synthesis (ISSS), Madrid, September 2000.
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C12. R. Lysecky, F. Vahid, T. Givargis.
Experiments with the Peripheral Virtual Component Interface.
International Symposium on System Synthesis (ISSS), Madrid, September 2000.
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C11. T. Givargis, F. Vahid.
Parameterized System Design.
International Workshop on Hardware/Software Codesign (CODES), San Diego, May 2000.
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C10. T. Givargis, F. Vahid, J. Henkel.
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design.
Design Automation and Test in Europe (DATE), Paris, March 2000.
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C9. R. Lysecky, F. Vahid, T. Givargis.
Techniques for Reducing Read Latency of Core Bus Wrappers.
Design Automation and Test in Europe (DATE), Paris, March 2000. Received the 2000 DATE Best Paper Award.pdf
C8. T. Givargis, F. Vahid. J. Henkel.
A Hybrid Approach for Core-Based System-Level Power Modeling.
Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, January 2000.
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C7. T. Givargis, J. Henkel, F. Vahid.
Interface and Cache Power Exploration for Core-Based Embedded System Design.
International Conference on Computer-Aided Design (ICCAD), San Jose, November 1999.
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C6. R. Lysecky, F. Vahid, T. Givargis, R. Patel.
Pre-Fetching for Improved Core Interfacing.
International Symposium on System Synthesis (ISSS), San Jose, November 1999.
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C5. J. Farrell, T. Givargis.
Experimental Differential GPS Reference Station Evaluation.
American Control Conference (ACC), San Diego, June 1999.
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C4. J. Farrell, T. Givargis. M. Barth.
Differential Carrier Phase GPS-Aided INS for Automotive Applications.
American Control Conference (ACC), San Diego, June 1999.
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C3. F. Vahid, T. Givargis.
The Case for a Configure-and-Execute Paradigm.
International Workshop on Hardware/Software Codesign (CODES), Rome, May 1999.
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C2. F. Vahid, T. Givargis.
Incorporating Cores into System-Level Specification.
International Symposium on System Synthesis (ISSS), Hsinchu, December 1998.
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C1. T. Givargis, F. Vahid.
Interface Exploration for Reduced Power in Core-Based Systems.
International Symposium on System Synthesis (ISSS), Hsinchu, December 1998.
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Workshop
W2. A. Nacul, M. Lajolo, T. Givargis.
Interface-Centric Abstraction Level for Rapid Hardware/Software Integration.
Forum on Specification and Design Languages (FDL), Lausanne, September 2005.
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W1. A. Haghighat, C. Lopes, T. Givargis, and A. Mandal.
Location-Aware Web System.
Workshop on Building Software for Pervasive Computing at the Object-Oriented Programming, Systems, Languages and Applications (OOPSLA) Conference, Vancouver, October 2004.
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